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april 2007 hyb25dc512800b[e/f] HYB25DC512160B[e/f] 512-mbit double-data-rate sdram ddr sdram rohs compliant products internet data sheet rev. 1.2
we listen to your comments any information within this document that yo u feel is wrong, unclear or missing at all? your feedback will help us to continuous ly improve the quality of this document. please send your proposal (including a reference to this document) to: techdoc@qimonda.com internet data sheet hyb25dc512[80/16]0b[e/f] double-data-rate sdram qag_techdoc_rev400 / 3.2 qag / 2006-08-07 2 04112007-fhbx-o8hd hyb25dc512800b[e/f], HYB25DC512160B[e/f] revision history: 2007-04, rev. 1.2 page subjects (major chang es since last revision) all adapted internet edition all editorial changes previous revision: 2006-09, rev. 1.11 all qimonda template update previous revision: 2006-09, rev. 1.1 internet data sheet rev. 1.2, 2007-04 3 04112007-fhbx-o8hd hyb25dc512[80/16]0b[e/f] double-data-rate sdram 1overview this chapter lists all main features of the product fa mily hyb25dc512[80/16]0b[e/f] and the ordering information. 1.1 features ? double data rate architecture: tw o data transfers per clock cycle ? bidirectional data strobe (dqs) is transmitted and received with data, to be used in capturing data at the receiver ? dqs is edge-aligned with data for reads and is center-aligned with data for writes ? differential clock inputs (ck and ck ) ? four internal banks for concurrent operation ? data mask (dm) for write data ? dll aligns dq and dqs transitions with ck transitions ? commands entered on each positive ck edge; data and data mask referenced to both edges of dqs ? burst lengths: 2, 4, or 8 ? cas latency: 1.5 (ddr200 only), 2, 2.5, 3 ? auto precharge option for each burst access ? auto refresh and self refresh modes ? ras-lockout supported t rap = t rcd ?7.8 s maximum average periodic refresh interval ? 2.5 v (sstl_2 compatible) i/o ? v ddq = 2.5 v 0.2 v (ddr200, ddr266, ddr333); v ddq = 2.6 v 0.1 v (ddr400b) ? v dd = 2.5 v 0.2 v (ddr200, ddr266, ddr333); v dd = 2.6 v 0.1 v (ddr400b) ? standard temperature range (0 c - +70 c) ? pg-tsopii-66 and pg-tfbga-60 packages ?rohs 1) compliant product types available (green product) table 1 performance 1) rohs compliant product: restriction of the use of certain hazar dous substances (rohs) in el ectrical and electronic equipment as defined in the directive 2002/95/ec issued by the european parliament and of the council of 27 january 2003. these substances include m ercury, lead, cadmium, hexavalent chromium, polybro minated biphenyls and polybrominated biphenyl ethers. product type speed code ?5 ?6 unit speed grade component ddr400b ddr333 ? max. clock frequency @cl3 f ck3 200 166 mhz @cl2.5 f ck2.5 166 166 mhz @cl2 f ck2 133 133 mhz internet data sheet rev. 1.2, 2007-04 4 04112007-fhbx-o8hd hyb25dc512[80/16]0b[e/f] double-data-rate sdram 1.2 description the 512-mbit double-data-rate sdram is a high-speed cmos, dynamic random-access memory containing 536,870,912 bits. it is internally configured as a quad-bank dram. the 512-mbit double-data-rate sdram uses a double-data-rate architecture to achieve high-speed operation. the double data rate architecture is essentially a 2n prefetch architecture with an interface designed to transfer two data words per clock cycle at the i/o pins. a single read or write access for the 512-mbit double-data-rate sdram effectively consists of a single 2n -bit wide, one clock cycle data transfer at the internal dram core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the i/o pins. a bidirectional data strobe (dqs) is transmitted externally, along with data, for use in data capt ure at the receiver. dqs is a strobe transmitted by the ddr sdram during reads and by th e memory controller during wr ites. dqs is edge-aligned with data for reads and center-aligned with data for writes. the 512-mbit double-data-rate sdram operates from a differential clock (ck and ck ; the crossing of ck going high and ck going low is referred to as the positive edge of ck). co mmands (address and control signal s) are registered at every positive edge of ck. input data is registered on both edges of dqs, and output data is refe renced to both edges of dqs, as well as to both edges of ck. read and write accesses to the ddr sdra m are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the registration of an active command, which is then followed by a read or write command. the addr ess bits registered coincident with the active command are used to select the bank and row to be accessed. the address bits registered coincident with the read or write command are used to select the bank and the starting column location for the burst access. the ddr sdram provides for programmable read or write burst lengths of 2, 4 or 8 locations. an auto precharge function may be enabled to provide a self-timed row pr echarge that is initiated at the end of the burst acce ss. as with standard sdrams, the pipelined, multibank architecture of ddr sdrams allows for concurrent operation, ther eby providing high effective bandwidth by hiding row precharge and activation time. an auto refresh mode is provided along with a power-saving power-down mode. all in puts are compatible with the industry standard for sstl_2. all outputs are sstl_2, class ii compatible. note: the functionality described and the timi ng specifications included in this dat a sheet are for the dll enabled mode of operation. internet data sheet rev. 1.2, 2007-04 5 04112007-fhbx-o8hd hyb25dc512[80/16]0b[e/f] double-data-rate sdram table 2 ordering information for lead-free products (rohs compliant) product type 1)2) 1) hyb : designator for memory components; 25dc: ddr sdrams at v ddq = 2.5 v; 512: 512 mbit density; 800/160: product variations 8 and 16; b: die revision; l: low power (available on request); f/c/e/t: package type fbga (lead & halogen free), fbga (lead c ontaining), tsop (lead & halogen free), and tsop (lead containing ). 2) please check with your qimonda representat ive that leadtime and availability of your preferred device type and version meet y our project requirements. organization cas-rcd-rp latencies clock (mhz) speed package note hyb25dc512800be?5 8 3-3-3 200 ddr400b pg-tsopii-66 3) 3) rohs compliant product: restriction of the use of certain hazar dous substances (rohs) in el ectrical and electronic equipment as defined in the directive 2002/95/ec issued by the european parliament and of the council of 27 january 2003. these substances include m ercury, lead, cadmium, hexavalent chromium, polybro minated biphenyls and polybrominated biphenyl ethers. HYB25DC512160Be?5 16 hyb25dc512800be?6 8 2.5-3-3 166 ddr333 hyb25dc512800bel?6 8 HYB25DC512160Be?6 16 HYB25DC512160Bel?6 16 hyb25dc512800bf?5 8 3-3-3 200 ddr400b pg-tfbga-60 HYB25DC512160Bf?5 16 hyb25dc512800bf?6 8 2.5-3-3 166 ddr333 HYB25DC512160Bf?6 16 internet data sheet rev. 1.2, 2007-04 6 04112007-fhbx-o8hd hyb25dc512[80/16]0b[e/f] double-data-rate sdram 2 configuration this chapter contains the chip configuration. 2.1 configuration of pg-tsopii-66 the ball configuration of a ddr s dram is listed by function in table 3 . the abbreviations used in the pin#/buffer# column are explained in table 4 and table 5 respectively. the chip numbering for tsop is depicted in figure 1 . table 3 ball configuration ball#/pin# name pin type buffer type function clock signals 45 ck i sstl clock signal 46 ck i sstl complementary clock signal 44 cke i sstl clock enable control signals 23 ras i sstl row address strobe 22 cas i sstl column address strobe 21 we i sstl write enable 24 cs i sstl chip select address signals 26 ba0 i sstl bank address bus 2:0 27 ba1 i sstl 29 a0 i sstl address bus 11:0 30 a1 i sstl 31 a2 i sstl 32 a3 i sstl 35 a4 i sstl 36 a5 i sstl 37 a6 i sstl 38 a7 i sstl 39 a8 i sstl 40 a9 i sstl 28 a10 i sstl ap i sstl 41 a11 i sstl internet data sheet rev. 1.2, 2007-04 7 04112007-fhbx-o8hd hyb25dc512[80/16]0b[e/f] double-data-rate sdram table 4 abbreviations for pin type table 5 abbreviations for buffer type 42 a12 i sstl address signal 12 note: module based on 256 mbit or larger dies nc nc ? note: module based on 128 mbit or smaller dies 17 a13 i sstl address signal 13 note: 1 gbit based module nc nc ? note: module based on 512 mbit or smaller dies power supplies 49 v ref ai ? i/o reference voltage 3, 9, 15, 55, 61 v ddq pwr ? i/o driver power supply 1, 18, 33 v dd pwr ? power supply 6, 12, 52, 58, 64 v ssq pwr ? power supply 34 v ss pwr ? power supply abbreviation description i standard input-only pin. digital levels o output. digital levels i/o i/o is a bidirectio nal input/output signal ai input. analog levels pwr power gnd ground nc not connected abbreviation description sstl serial stub terminalted logic (sstl2) lv-cmos low voltage cmos cmos cmos levels od open drain. the corresponding pin has 2 operat ional states, active low and tristate, and allows multiple devices to share as a wire-or ball#/pin# name pin type buffer type function internet data sheet rev. 1.2, 2007-04 8 04112007-fhbx-o8hd hyb25dc512[80/16]0b[e/f] double-data-rate sdram figure 1 chip configuration pg-tsopii-66 0 3 3 ' 9 ' ' ' 4 9 ' ' 4 9 6 6 4 ' 4 ' 4 9 ' ' 4 ' 4 ' 4 ' 4 ' 4 9 6 6 4 ' 4 9 ' ' 4 1 & |